SUNNYVALE, CA — (Marketwire) — 05/29/12 — ., the leading provider of software products that accelerate Early Functional Verification and Advanced Sign-off of electronic designs, announced today the release of version 4.1 of its (CDC) analyzer and the release of version 1.5.1 of its tool. These new releases provide significant advances over the 2011 versions of the software.Real Intent-s software products solve challenging SoC verification and sign-off design problems with speed that no ot
Demos Set for Design Automation Conference, June 4-6, San Francisco, Booth 2900
Interoperability Between Aceplorer and Synopsys System-Level Design Solutions Enables Finding the Right Trade-Off Between Power and Performance
Mr. Aynsley Will Be Recognized for Contributions to SystemC at Organization-s DVCon on February 27, 2012
SystemC Supports Efficient, High-Level Design of Complex Integrated Circuits and Systems-on-Chips
Sessions on Monday, February 27, 2012 at the DoubleTree Hotel, San Jose, Calif. Focus on EDA & IP Standards
Use of SFT-s R3D Software for XH018 Process Design Kit Improves High-Voltage and Driver Characteristics of Mixed-Signal SOC Designs
Aceplorer Optimizes for Power and Thermal Analysis at the Architectural Level
