back to homepage

Tag "eda"

REMINDER: Docea Power to Highlight Co-Exploration With System-Level Performance Analysis Tools at SNUG Silicon Valley Designer Community Expo 0

Interoperability Between Aceplorer and Synopsys System-Level Design Solutions Enables Finding the Right Trade-Off Between Power and Performance

Read More

REMINDER: Docea Power to Highlight Co-Exploration With System-Level Performance Analysis Tools at SNUG Silicon Valley Designer Community Expo 0

Interoperability Between Aceplorer and Synopsys System-Level Design Solutions Enables Finding the Right Trade-Off Between Power and Performance

Read More

Docea Power to Highlight Co-Exploration With System-Level Performance Analysis Tools at SNUG Silicon Valley Designer Community Expo 0

Interoperability Between Aceplorer and Synopsys System-Level Design Solutions Enables Finding the Right Trade-Off Between Power and Performance

Read More

Calypto Adds Christopher Mausler as CFO 0

SANTA CLARA, CA — (Marketwire) — 03/06/12 — , Inc., the leader in Register Transfer Level (RTL) power optimization and Electronic System Level (ESL) hardware design, today announced that Chris Mausler has joined the company as Chief Financial Officer (CFO). Before joining Calypto, Chris was the vice president of Finance, corporate controller and acting CFO for Ubicom, Inc., a networking and multimedia semiconductor start up."These are exciting times for Calypto. We have just completed

Read More

John Aynsley Is First to Receive Accellera Systems Initiative Technical Excellence Award 0

Mr. Aynsley Will Be Recognized for Contributions to SystemC at Organization-s DVCon on February 27, 2012

Read More

Accellera Systems Initiative Announces „Accellera Systems Initiative Day“ at Its 2012 Design and Verification Conference and Exhibition (DVCon) 0

Sessions on Monday, February 27, 2012 at the DoubleTree Hotel, San Jose, Calif. Focus on EDA & IP Standards

Read More

X-FAB Uses Silicon Frontline-s Post-Layout Extraction Software to Enhance Its Advanced Mixed-Signal Process Design Kit (PDK) 0

Use of SFT-s R3D Software for XH018 Process Design Kit Improves High-Voltage and Driver Characteristics of Mixed-Signal SOC Designs

Read More

Calypto Exec, Anmol Mathur, Speaks on Power Aware Design and Verification at IEEE ASIC Conference 0

XIAMEN, CHINA — (Marketwire) — 10/20/11 — ASICON 2011, Inc., the leader in Electronic System Level (ESL) hardware design and Register Transfer Level (RTL) power optimization, announced that its CTO Ammol Mathor will give a tutorial on A New Approach for Power Aware Design and Verification Using Sequential Analysis Technology at the 9th International Conference on ASIC () in Xiamen, China.14:00-15:30, October 25, 2011
Room A, Xiamen International Seaside Hotel
Xiamen, ChinaPower is a key de

Read More

REMINDER: Calypto Attends ARM TechCon, Offers Class on RTL Verification, Invites Attendees to Learn More About High Level Electronic Design Synthesis, Power Optimization and Equivalence Checking 0

SANTA CLARA, CA — (Marketwire) — 10/20/11 — ARM TechCon 2011, October 25, Santa Clara, CA, Inc., the leader in Electronic System Level (ESL) hardware design and Register Transfer Level (RTL) power optimization, announced that Nikhil Sharma, Vice President of Applications Engineering and Services, will speak on Formal Verification of RTL Changes for Intellectual Property (IP) Hardening at 2011, in Santa Clara, CA, USA, Tuesday, October 25. In addition, during the ARM TechCon Expo on the sam

Read More