SAN FRANCISCO, CA — (Marketwire) — 05/31/12 –At the (DAC), , a leading provider of EDA software that accelerates field-programmable gate array (FPGA) implementation, will showcase its Blue Pearl Software Suite-s interoperability with tools and flows from other leading FPGA ecosystems players — Xilinx Vivado Design Suite and Synopsys Synplify Pro FPGA synthesis software.The provides Register Transfer Level (RTL) analysis and includes linting, clock domain crossing (CDC) and automatic Synops
SUNNYVALE, CA — (Marketwire) — 05/29/12 — ., the leading provider of software products that accelerate Early Functional Verification and Advanced Sign-off of electronic designs, announced today the release of version 4.1 of its (CDC) analyzer and the release of version 1.5.1 of its tool. These new releases provide significant advances over the 2011 versions of the software.Real Intent-s software products solve challenging SoC verification and sign-off design problems with speed that no ot
SANTA CLARA, CA — (Marketwire) — 03/06/12 — , Inc., the leader in Register Transfer Level (RTL) power optimization and Electronic System Level (ESL) hardware design, today announced that Chris Mausler has joined the company as Chief Financial Officer (CFO). Before joining Calypto, Chris was the vice president of Finance, corporate controller and acting CFO for Ubicom, Inc., a networking and multimedia semiconductor start up."These are exciting times for Calypto. We have just completed
XIAMEN, CHINA — (Marketwire) — 10/20/11 — ASICON 2011, Inc., the leader in Electronic System Level (ESL) hardware design and Register Transfer Level (RTL) power optimization, announced that its CTO Ammol Mathor will give a tutorial on A New Approach for Power Aware Design and Verification Using Sequential Analysis Technology at the 9th International Conference on ASIC () in Xiamen, China.14:00-15:30, October 25, 2011 Room A, Xiamen International Seaside Hotel Xiamen, ChinaPower is a key de
SANTA CLARA, CA — (Marketwire) — 10/20/11 — ARM TechCon 2011, October 25, Santa Clara, CA, Inc., the leader in Electronic System Level (ESL) hardware design and Register Transfer Level (RTL) power optimization, announced that Nikhil Sharma, Vice President of Applications Engineering and Services, will speak on Formal Verification of RTL Changes for Intellectual Property (IP) Hardening at 2011, in Santa Clara, CA, USA, Tuesday, October 25. In addition, during the ARM TechCon Expo on the sam
