Collaboration With FPGA Partitioning and Verification Software Providers Addresses Demand for Reliable, Cost-Effective Verification of Complex, High Density Designs
SOPHIA ANTIPOLIS, FRANCE — (Marketwire) — 10/03/12 –At the Sophia Antipolis MicroElectronics forum ( 2012), , a leading provider of EDA software that accelerates field-programmable gate array (FPGA) implementation, and , a provider of functional verification and test software for accelerated verification of FPGA Intellectual Property (IP) blocks and designs, are presenting a tutorial on Best FPGA Design Practices. During , the companies will be demonstrating solutions at the ADACYS Stand # 20
SOPHIA ANTIPOLIS, FRANCE — (Marketwire) — 10/02/12 –At the Sophia Antipolis MicroElectronics forum ( 2012), , a leading provider of EDA software that accelerates field-programmable gate array (FPGA) implementation, and , a provider of functional verification and test software for accelerated verification of FPGA Intellectual Property (IP) blocks and designs, are presenting a tutorial on Best FPGA Design Practices. During , the companies will be demonstrating solutions at the ADACYS Stand # 20
