SOPHIA ANTIPOLIS, FRANCE — (Marketwire) — 10/03/12 —
At the Sophia Antipolis MicroElectronics forum ( 2012), , a leading provider of EDA software that accelerates field-programmable gate array (FPGA) implementation, and , a provider of functional verification and test software for accelerated verification of FPGA Intellectual Property (IP) blocks and designs, are presenting a tutorial on Best FPGA Design Practices. During , the companies will be demonstrating solutions at the ADACYS Stand # 20.
Session 3: Tutorial: Best FPGA Design Practices 13h30-15H00, Wednesday, 3 October, 2012
Demos: ADACSYS Stand # 20
CICA 2229 Route des Crêtes 06560 Sophia Antipolis-France
To schedule a meeting with Blue Pearl, please email . For more information, please visit . For more information about SAME 2012, please visit .
is a start-up specializing in FPGA-based High Performance Computing (HPC) solutions. ADACSYS provides tools to accelerate the physical tests and debug of embedded applications for aeronautics, FPGA designs and ASIC FPGA-based prototyping markets.
provides next generation EDA software that uses new and innovative technology to reduce design flow iterations and increase designer productivity early in the digital design flow. checks RTL designs for functional errors and automatically generates comprehensive and accurate Synopsys Design Constraints (SDC) to improve quality of results (QoR) and reduce FPGA and ASIC design risks.
Press Contact: Georgia Marszalek ValleyPR LLC for Blue Pearl Software +1 650 345 7477
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