Company Announces New Glasswing(TM) Family of SerDes Ideal for Chip-to-Chip Links Inside a Package
Collaboration With FPGA Partitioning and Verification Software Providers Addresses Demand for Reliable, Cost-Effective Verification of Complex, High Density Designs
SAN FRANCISCO, CA — (Marketwire) — 05/31/12 –At the (DAC), , a leading provider of EDA software that accelerates field-programmable gate array (FPGA) implementation, will showcase its Blue Pearl Software Suite-s interoperability with tools and flows from other leading FPGA ecosystems players — Xilinx Vivado Design Suite and Synopsys Synplify Pro FPGA synthesis software.The provides Register Transfer Level (RTL) analysis and includes linting, clock domain crossing (CDC) and automatic Synops
SUNNYVALE, CA — (Marketwire) — 05/29/12 — ., the leading provider of software products that accelerate Early Functional Verification and Advanced Sign-off of electronic designs, announced today the release of version 4.1 of its (CDC) analyzer and the release of version 1.5.1 of its tool. These new releases provide significant advances over the 2011 versions of the software.Real Intent-s software products solve challenging SoC verification and sign-off design problems with speed that no ot
