XIAMEN, CHINA — (Marketwire) — 10/20/11 — ASICON 2011
, Inc., the leader in Electronic System Level (ESL) hardware design and Register Transfer Level (RTL) power optimization, announced that its CTO Ammol Mathor will give a tutorial on A New Approach for Power Aware Design and Verification Using Sequential Analysis Technology at the 9th International Conference on ASIC () in Xiamen, China.
14:00-15:30, October 25, 2011 Room A, Xiamen International Seaside Hotel Xiamen, China
Power is a key design goal in current System-On-Chip (SOC) designs. Almost all transformations that significantly lower design power at the RTL and micro-architectural levels are sequential in nature — they change the behavior of the design in time. Sequential clock gating, memory gating, use of sleep modes for static power reduction, power gating and dynamic voltage scaling can all change the behavior of the design. This tutorial focuses on techniques for power-aware SOC design, and sequential equivalence checking and how it-s used in design flows from system-level models to RTL.
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Calypto-s HLS (High Level Synthesis), (Sequential Logic Equivalence Checking) and platforms are used by seven out of the top ten semiconductor companies and over 100 leading consumer electronics companies worldwide. Calypto-s products enable ESL design, dramatically improve design quality and reduce power consumption of SOC devices.
, Inc. is the leader in ESL hardware design and RTL power optimization. Calypto, whose customers include Fortune 500 companies worldwide, is a member of the ARM Connected Community, Cadence Connections program, the IEEE-SA, Synopsys SystemVerilog Catalyst Program, the Mentor Graphics OpenDoor program, Si2 and is an active participant in the Power Forward Initiative. Calypto has offices in Europe, India, Japan and North America. More information can be found at .
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