SANTA CLARA, CA — (Marketwire) — 10/29/12 —
, the provider of EDA software that accelerates RTL signoff for FPGA designs
Demonstrations of the of the at
Oct. 31-Nov. 1, 2012, stand TT2 Santa Clara Convention Center Santa Clara, California
The works with the Xilinx Vivado Design Suite running on Windows platforms. It includes linting, CDC analysis and automatic SDC generation. Its generated SDCs automate the synthesis and place and route phases of FPGA design implementation, and reduce iterations and overall design time. Its Visual Verification Environment makes it easy to use.
The company-s collaboration with Synopsys offers an optimized flow that works with Synopsys- Synplify Pro FPGA synthesis software. Verilog, VHDL and SystemVerilog designers can automatically generate an exhaustive set of constraints that address false and multi-cycle paths that are compatible with Synopsys- synthesis flow.
Please click on the following links to sign up for a and . For information, on Blue Pearl-s longest path analysis, please to read our article . For information on how Blue Pearl enables SoC RTL analysis, to read our white paper, . To register for ARM TechCon, please visit .
Blue Pearl Software, Inc. is a member of the , and provides EDA software that accelerates RTL signoff for FPGA designs. The checks RTL designs for functional errors and automatically generates comprehensive and accurate Synopsys Design Constraints (SDCs) to improve Quality of Results (QoR) and reduce design risks.
Visit Blue Pearl Software at .
Acronyms CDC: Clock Domain Crossing EDA: Electronic Design Automation FPGA: Field Programmable Gate Array QoR: Quality of Results RTL: Register Transfer Level SDC: Synopsys Design Constraints SoC: System-on-Chip
Visual Verification Environment is a trademark of Blue Pearl Software, Inc. All other trademarks are property of their respective owners.
Press Contact: Georgia Marszalek ValleyPR LLC for Blue Pearl Software +1-650.345.7477
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